Measuring method of loss for optical waveguides by use of a rectangular glass probe

The use of a glass-plate probe of rectangular shape is proposed for the measurement of transmission loss in thin-film optical waveguides. The light-collecting window is of a thin rectanglar shape perpendicular to the light streak, while the conventional fiber probe has a very small circular face. This transversely elongated form results in a great improvement of the mechanical tolerance for the probe movement in the vertical as well as the transverse direction. Theoretical investigation is also presented in reasonable agreement with the experiments

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 μm2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning

A power optimization method considering glitch reduction by gate sizing

We propose a power optimization method considering glitch re-duction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark cir-cuits with a 0.5 m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimum-sized circuits.

Chemical modification utilizing a terminal structure exposed on the specific surface of polymer-metal complex nanocrystals

It has been difficult to selectively modify the surface of molecular crystals by chemical reactions because they usually have no reaction points on their surfaces. In this paper, focusing on the unique nanocrystal surface of the polymer metal complex (PMC) [{Cu(2)(μ-Br)(2)(PPh(3))(2)}(μ-bpy)](n) having an exposed reactive terminal chain, we successfully modified the surface of PMC nanocrystals (NCs) through an alkylation reaction. Interestingly, after the alkylation reaction, the luminescence spectrum of PMC NCs blue-shifted, and the luminescence quantum yield increased. PMC NCs with a large specific surface area showed optically peculiar or characteristic properties compared with the corresponding bulk crystals. PMC NCs have high potential as a new class of luminescent materials due to their surface effect

Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation

We are developing field-programmable gate arrays (FPGAs) with a new non-volatile switch called via-switch. In via-switch FPGAs (VS-FPGAs), the via-switches required for reconfiguration are placed in the routing layer so that the entire transistor layer can be utilized for computing, and higher implementation density can be achieved compared to conventional SRAM FPGAs. Furthermore, since arithmetic units and memories for computing can be placed under the via-switch crossbar for routing, large-scale parallel operations can be realized where the memory and the arithmetic unit are adjacent to each other. These features enable operation with high energy efficiency. This article reports 65 nm prototype fabrication results and predicted the performance of the VS-FPGA designed for AI applications. We also present the developed application mapping flow and crossbar programming method. The VS-FPGA closes the gap between FPGA and application-specific integrated circuits (ASIC) with the performance advantage of the via-switch and via-switch copy scheme for FPGA-to-ASIC migration, contributing to the expansion of the FPGA usage